MOSFET test structure for capacitance-voltage measurements
US6472233B1 · kind B1 · utility
20Cited by
9References
12Claims
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Key dates
| Filing date | Jun 5, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Jun 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus and method used in extracting polysilicon gate doping from C−V analysis in strong inversion, especially for ultrathin gate oxides. For sub-20-angstrom oxide MOS devices, transistors with channel lengths less than about 10 &mgr;m are connected in parallel to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length is estimated using a transmission-line-model of the terminal capacitance, which accounts for the non-negligible gate tunneling current and finite channel resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.