Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers
US6472317B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2001 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Apr 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A second low k dielectric layer is formed on the first low k dielectric layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Further etching of the first dielectric layer is prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.