Passive multiplexor test structure for integrated circuit manufacturing
US6475871B1 · kind B1 · utility
18Cited by
36References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Nov 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A test structure for analyzing failures due to fabrication induced defects in integrated circuits includes a matrix of bit cells formed by word lines and bit lines. An associated word line probe pad is electrically connected to each word line and an associated bit line probe pad electrically connected to each bit line. A test structure is electrically connected between a word line and a bit line of an associated bit cell. Each test structure has at least one variable attribute which is used to detect defects and create yield models.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.