Larg Weiland
95Patents
10h-index
35Co-inventors
78Inventor score
Filing activity: Nov 17, 2000 → Oct 31, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6834375B1 | System and method for product yield prediction using a logic characterization vehicle | Electricity | 222 | Expired |
| US6901564B2 | System and method for product yield prediction | Electricity | 127 | Expired |
| US7174521B2 | System and method for product yield prediction | Electricity | 20 | Expired |
| US6475871B1 | Passive multiplexor test structure for integrated circuit manufacturing | Electricity | 18 | Expired |
| US9799575B2 | Integrated circuit containing DOEs of NCEM-enabled fill cells | Electricity | 17 | Active |
| US9805994B1 | Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads | Electricity | 13 | Active |
| US9870962B1 | Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Electricity | 12 | Active |
| US6787800B2 | Test vehicle with zig-zag structures | Physics | 11 | Expired |
| US9627370B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 11 | Active |
| US7024642B2 | Extraction method of defect density and size distributions | Electricity | 10 | Expired |
| US7356800B2 | System and method for product yield prediction | Electricity | 8 | Active |
| US10593604B1 | Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells | Electricity | 8 | Active |
| US7373625B2 | System and method for product yield prediction | Electricity | 7 | Active |
| US7197726B2 | Test structures for estimating dishing and erosion effects in copper damascene technology | Electricity | 6 | Expired |
| US7673262B2 | System and method for product yield prediction | Electricity | 6 | Active |
| US9627371B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells | Electricity | 5 | Active |
| US10978438B1 | IC with test structures and E-beam pads embedded within a contiguous standard cell area | Electricity | 4 | Active |
| US9691672B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells | Electricity | 4 | Active |
| US10096530B1 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells | Electricity | 3 | Active |
| US10199283B1 | Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage | Electricity | 3 | Active |
| US9773774B1 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells | Electricity | 3 | Active |
| US7154115B2 | Zoom in pin nest structure, test vehicle having the structure, and method of fabricating the structure | Electricity | 3 | Expired |
| US9741703B1 | Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells | Electricity | 3 | Active |
| US9786648B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 2 | Active |
| US9761575B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.