Patent · US Expired

Circuit configuration for programming a delay in a signal path

US6480024B2 · kind B2 · utility

5Cited by

4References

8Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Stefan Dietrich · Potsdam, DE
Thomas Hein · Hersbruck, DE
Patrick Heyne · Hersbruck, DE
Michael Markert · Augsburg, DE
Thilo Marx · Villingen-Schwenningen, DE
Torsten Partsch · San Jose, US
Sabine Kieser · Hausham, DE
Peter Schrogmeier · Hersbruck, DE
Michael Sommer · Raubling, DE
Christian Weis · Scheidegg, DE

Key dates

Filing date	Oct 19, 2001
Grant date	Nov 12, 2002
Priority date	—
Expiry date	Oct 19, 2021

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00091
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.