Method of fabricating a semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer
US6503803B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Jan 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of fabricating a semiconductor device including forming an insulating film on a silicon substrate; forming a contact hole in the insulating film; depositing a titanium film to be in contact with the silicon substrate in the contact hole; and causing a heat reaction between the titanium film and the silicon substrate such that the titanium film is subjected to silicide reaction with the thickness 4 nm to 48 nm or, more preferably, with the thickness of 8 nm to 34 nm. In the instance where the contact hole is filled with doped polycrystal silicon material, the titanium film is deposited to be in contact with the polycrystal silicon in the contact hole. The silicon substrate/silicon body may have at least a MISFET formed thereon in which case the contact hole is formed to expose an active region of the MISFET, as one example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.