Semiconductor memory device and defect remedying method thereof
US6515913B2 · kind B2 · utility
12Cited by
19References
5Claims
0Family size
Assignee
Inventors
- Kazuhiko Kajigaya
- Kazuyuki Miyazawa
- Manabu Tsunozaki
- Kazuyoshi Oshima
- Takashi Yamazaki
- Yuji Sakai
- Jiro Sawada
- Yasunori Yamaguchi
- Tetsurou Matsumoto
- Shinji Udo
- Hiroshi Yoshioka
- Hirokazu Saito
- Mitsuhiro Takano
- Makoto Morino
- Sinichi Miyatake
- Eiji Miyamoto
- Yasuhiro Kasama
- Akira Endo
- Ryoichi Hori
- Jun Etoh
- Masashi Horiguchi
- Shinichi Ikenaga
- Atsushi Kumata
Key dates
| Filing date | Dec 4, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Dec 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.