Integrated circuit and method
US6528888B2 · kind B2 · utility
12Cited by
11References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Feb 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.