Sense amplifiers having reduced Vth deviation
US6538945B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 18, 2002 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Jan 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers. In a DRAM chip, P+-type gate PMOSs of P+-type polysilicon gates each having a low impurity density of channel and N+-type gate NMOSs of N+-type polysilicon gates are used in a sense amplifier cross coupling section to further increase substrate voltages of the PMOSs and to decrease substrate voltages of the NMOS. For this reason, a deviation of threshold voltage caused by channel implantation is reduced, and a small signal generated on a data line at a read operation of a low-potential memory array is accurately sensed and amplified by a sense amplifier. In addition, the threshold voltages are increased by a substrate bias effect, and a leakage current in a sense amplifier data holding state is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.