Integrated memory and corresponding operating method
US6538950B2 · kind B2 · utility
1Cited by
5References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Jul 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.