Bi-layer trim etch process to form integrated circuit gate structures
US6541360B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Apr 30, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/952
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etching the organic underlayer to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of organic underlayer. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or the aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.