Dual silicon-on-insulator device wafer die
US6558994B2 · kind B2 · utility
31Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Jul 19, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/967
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.