Process for forming fully silicided gates
US6562718B1 · kind B1 · utility
39Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2000 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Dec 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28097
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.