Structure and method for a high-performance electronic packaging assembly
US6570248B1 · kind B1 · utility
310Cited by
72References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2001 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Aug 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved structure and method are provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various intergrated circuit devices located on the opposing surfaces of the silicon interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.