Semiconductor integrated circuit device and process for manufacturing the same
US6573546B2 · kind B2 · utility
1Cited by
2References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 7, 2001 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Aug 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.