Package structure for a photosensitive chip
US6590269B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2002 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Apr 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73265
Abstract
A package structure for a photosensitive chip includes a substrate having an upper surface and a lower surface, and a frame layer having a first surface and a second surface. The frame layer is formed on the substrate by way of injection molding with the first surface contacting the upper surface. A cavity is formed between the substrate and the frame layer. The second surface is formed with a depression in which plural projections each having a suitable height are formed. The frame layer is formed directly on the substrate by way of injection molding. The package structure further includes a photosensitive chip arranged within the cavity, a plurality of wires for connecting the substrate to the photosensitive chip, and a transparent layer rested on the projections within the depression. Accordingly, the yield can be improved and the manufacturing processes can be facilitated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.