Staggered bitline strapping of a non-volatile memory cell

US6593606B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Mark Randolph · San Jose, US
• Shane Hollmer · Grass Valley, US
• Pau-Ling Chen · Saratoga, US
• Richard Fastow · Cupertino, US

Key dates

• Filing date: Nov 22, 2000
• Grant date: Jul 15, 2003
• Expiry date: May 19, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

An array of memory cells includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines, wherein M=2, 3, 4, 5, . . . wherein each of the M bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=1, 2, 3, . . . , wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts, and wherein contacts overlying a first bit line are staggered with respect to contacts overlying a second bit line that is adjacent to the first bit line.