Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance
US6613652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2001 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | May 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76289
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.