Method for evaluating decoupling capacitor placement for VLSI chips
US6618844B2 · kind B2 · utility
4Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Feb 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.