Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer
US6630383B1 · kind B1 · utility
46Cited by
9References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 17, 2002 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Oct 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/666
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method of making a gate stack semiconductor device is disclosed. The method comprises the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer and subjecting the n-type polysilicon layer to nitridation, and then forming a p-type polysilicon layer over the nitridated n-type polysilicon layer; and forming a high-K insulating layer over the p-type polysilicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.