Semiconductor analysis arrangement and method therefor

US6635839B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Glen Gilfeather · Helotes, US
• Srikar V. Chunduri · Austin, US
• Brennan V. Davis · Austin, US
• David H. Eppes · Austin, US
• Victoria J. Bruce · Austin, US
• Michael R. Bruce · Austin, US
• Rosalinda M. Ring · Austin, US
• Daniel L. Stone · Austin, US

Key dates

• Filing date: Apr 19, 2001
• Grant date: Oct 21, 2003
• Expiry date: Apr 19, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/311
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Semiconductor die analysis is enhanced using a system that is adapted to perturb a die in a test chamber and to detect a response from the die to the perturbation. According to an example embodiment of the present invention, a semiconductor die analysis system includes a test chamber and a docking arrangement adapted to dock with the test chamber. A die is held in the docking arrangement and is presented inside of the test chamber when the docking arrangement is docked with the chamber. Two or more perturbation devices are used to perturb the die, and controller is adapted to control the perturbation. A data acquisition arrangement receives data from the die in response to the perturbation, and the data is used for analyzing the die.