Memory architecture
US6639824B1 · kind B1 · utility
7Cited by
2References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Sep 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage generator (VVG) for generating an output voltage having a different voltage level depending on a location of an addressed memory cell within the memory group is provided. By providing different voltage levels for reads and/or writes, signal loss caused by capacitances which is dependent on the location of the memory cell within the group can be avoided. This improves read and/or write operations in series memory architectures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.