Process for producing semiconductor integrated circuit device
US6693001B2 · kind B2 · utility
8Cited by
18References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2000 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Feb 4, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.