Replacing layers of an intergate dielectric layer with high-K material for improved scalability
US6693321B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2002 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | May 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/681
Abstract
A method of making and a semiconductor device formed on a semiconductor substrate having an active region. The semiconductor device includes a gate dielectric layer disposed on the semiconductor substrate. A floating gate is formed on the gate dielectric layer and defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. A control gate is formed above the floating gate. Further, the semiconductor device includes an intergate dielectric layer interposed between the floating gate and the control gate. The intergate dielectric layer including a first, a second and a third layers. The first layer formed on the floating gate. The second layer formed on the first layer. The third layer formed on the second layer. Each of the first, second and third layers has a dielectric constant greater than SiO2 and an electrical equivalent thickness of less than about 50 angstroms (å) of SiO2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.