Copper interconnect with improved barrier layer
US6727592B1 · kind B1 · utility
10Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2002 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Feb 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 å, and/or as discontinuous regions of clusters of atoms on sides of the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.