Self-aligned semiconductor interconnect barrier and manufacturing method therefor
US6734559B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2000 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Mar 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligned semiconductor interconnect barrier between channels and vias is provided which is self-aligned and made of a metallic barrier material. A channel is conventionally formed in the semiconductor dielectric, lined with a first metallic barrier material, and filled with a conductive material. A recess is etched to a predetermined depth into the conductive material, and the second metallic barrier material is deposited and removed outside the channel. This leaves the conductive material totally enclosed in metallic barrier material. The metallic barrier material is selected from metals such as tantalum, titanium, tungsten, compounds thereof, alloys thereof, and combinations thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.