High density dual bit flash memory cell with non planar structure
US6735123B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Jul 11, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual bit dielectric memory cell comprises a substrate with a source region and a drain region implanted on opposing sides of a central channel region. A multilevel charge trapping dielectric is positioned on the substrate above the central channel region and includes a central region between an opposing source lateral region and a drain lateral region. A control gate is positioned above the multilevel charge trapping dielectric. The multilevel charge trapping dielectric comprises a tunnel dielectric layer adjacent the substrate, a top dielectric adjacent the control gate, and a charge trapping dielectric positioned there between. The thickness of the tunnel dielectric layer in the central region is greater than a thickness of the tunnel dielectric layer in each of the source lateral region and the drain lateral region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.