Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions
US6743689B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2003 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Jan 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6743
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.