Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices
US6753219B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 23, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Aug 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.