Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process

US6759179B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Khoi A. Phan · San Jose, US
• Jeffrey P. Erhardt · San Jose, US
• Jerry Cheng · Milpitas, US
• Richard Bartlett · Sunnyvale, US
• Anthony P. Coniglio · San Jose, US
• Wolfram Grundke · Dresden, DE
• Carol M. Bradway · Austin, US
• Daniel E. Sutton · Austin, US
• Martin Mazur · Pulsnitz, DE

Key dates

• Filing date: Jan 16, 2002
• Grant date: Jul 6, 2004
• Expiry date: Apr 10, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/28035
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein, including special vapor prime and development operations.