Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM
US6762974B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2003 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Mar 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.