Pre-charge method for reading a non-volatile memory cell
US6788583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2002 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Apr 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.