Method and structure for high capacitance memory cells
US6812513B2 · kind B2 · utility
83Cited by
20References
24Claims
0Family size
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Key dates
| Filing date | Feb 3, 2003 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Feb 3, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/943
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method and structure for high capacitance memory cells is provided. The method includes forming a trench capacitor in a semiconductor substrate. A self-structured mask is formed on the interior surface of the trench. The interior surface of the trench is etched to form an array of silicon pillars. The self-structured mask is removed. Then an insulator layer is formed on the array of silicon pillars. A polycrystalline semiconductor plate extends outwardly from the insulator layer in the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.