Partial array self-refresh
US6834022B2 · kind B2 · utility
36Cited by
3References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2003 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Nov 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored automatically by the memory device during a memory operation mode or manually by a user during a programming mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.