Circuit device with at least partial packaging and method for forming

US6838776B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• George R. Leal · Cedar Park, US
• Jie Zhao · Seoul, KR
• Edward R. Prack · Phoenix, US
• Robert J. Wenzel · New Port Richey, US
• Brian D. Sawyer · Atlanta, US
• David G. Wontor · Allen, US
• Marc Alan Mangrum · Austin, US

Key dates

• Filing date: Apr 18, 2003
• Grant date: Jan 4, 2005
• Expiry date: Apr 18, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3025
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.