Redundancy in series grouped memory architecture
US6856560B2 · kind B2 · utility
1Cited by
7References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2002 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Sep 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved redundancy scheme for chained memory architecture is disclosed. The redundancy scheme comprises including redundant cells as part of the memory chain. As such, a redundant cell is used to repair a defective cell within the chain. This eliminates the need in conventional chained architecture to replace the whole memory block when there is a defective cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.