Semiconductor substrate with trenches for reducing substrate resistance
US6858471B1 · kind B1 · utility
6Cited by
4References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2002 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Jan 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the present invention, a method for fabricating semiconductor devices comprises forming an active region about a front-side of a substrate. A plurality of trenches are then formed about a back-side of the substrate. A grid of banks separates the trenches. A conductive material is then applied to the back-side of the substrate. The trenches and the conductive material act to reduce the on-state resistance of the substrate and enhance thermal conductivity, while the grid of banks maintains the structural strength of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.