Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
US6861307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Jul 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.