MRAM architecture

US6888743B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Mark Durlam · Chandler, US
• Thomas Andre · Austin, US
• Brian R. Butcher · Gilbert, US
• Mark Deherrera · Tempe, US
• Bradley N. Engel · Chandler, US
• Bradley J. Garni · Austin, US
• Gregory W. Grynkewich · Gilbert, US
• Joseph J. Nahas · Austin, US
• Nicholas Rizzo · Gilbert, US
• Saied N. Tehrani · Tempe, US
• Clarance J. Tracy · Tempe, US

Key dates

• Filing date: Dec 27, 2002
• Grant date: May 3, 2005
• Expiry date: Mar 24, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/16
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.