Advanced RF enhancement-mode FETs with improved gate properties

US6893947B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Marino J. Martinez · Phoenix, US
• Ernest Schirmann · Lake Zurich, US
• Olin L. Hartin · Chandler, US
• Colby Greg Rampley · Phoenix, US
• Mariam Sadaka · Austin, US
• Charles E. Weitzel · Mesa, US
• Julio C. Costa · Oak Ridge, US

Key dates

• Filing date: Jun 25, 2002
• Grant date: May 17, 2005
• Expiry date: Nov 21, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/852
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.