Method of protecting a memory array from charge damage during fabrication
US6897110B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2002 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | May 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.