ESD implant following spacer deposition
US6900085B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2001 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Jun 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.