Method for fabricating a gate structure of a field effect transistor
US6924191B2 · kind B2 · utility
409Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Aug 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating features on a substrate having reduced dimensions. The features are formed by defining a first mask on regions of the substrate. The first mask is defined using lithographic techniques. A second mask is then conformably formed on one or more sidewalls of the first mask. The features are formed on the substrate by removing the first mask and then etching the substrate using the second mask as an etch mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.