Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence
US6930034B2 · kind B2 · utility
25Cited by
5References
19Claims
0Family size
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Key dates
| Filing date | Dec 27, 2002 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Apr 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating low k and ultra-low k multilayer interconnect structures on a substrate includes: a set of interconnects separated laterally by air gaps; forming a support layer in the via level of a dual damascene structure that is only under the metal line; removing a sacrificial dielectric through a perforated bridge layer that connects the top surfaces of the interconnects laterally; performing multilevel extraction of a sacrificial layer; sealing the bridge in a controlled manner; and decreasing the effective dielectric constant of a membrane by perforating it using sub-optical lithography patterning techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.