Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions
US6954394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2002 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Oct 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The preferred embodiments described herein relate to an integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells arranged in L layers stacked vertically above one another in a single integrated circuit. A memory cell layer in the memory array is selected, and one of N sets of memory-cell-layer-dependent writing conditions and/or one of K sets of memory-cell-layer-dependent reading conditions is selected based on the selected memory cell layer. In another preferred embodiment, a temperature of an integrated circuit is measured, and a set of writing conditions and/or a set of reading conditions is selected based on the measured temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.