Stress-relief layer for semiconductor applications

US6960835B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Hans-Joachim Barth · Munich, DE
• Erdem Kaltalioglu · Newburgh, US
• Mark Hoinkis · Fishkill, US
• Gerald Friese · Munich, DE
• Pak K. Leung · Kowloon, CN

Key dates

• Filing date: Oct 30, 2003
• Grant date: Nov 1, 2005
• Expiry date: Oct 30, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias.