Memory device and method using positive gate stress to recover overerased cell
US6967873B2 · kind B2 · utility
34Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2003 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | May 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/345
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.