Self-aligned mask to reduce cell layout area

US6974770B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• International Business Machines Corporation · US

Inventors

• Gregory Costrini · Hopewell Junction, US
• Kia-Seng Low · Hopewell Junction, US
• David L. Rath · Stormville, US
• Michael C. Gaidis · Yorktown Heights, US
• Walter Glashauser · Munich, DE

Key dates

• Filing date: Jun 20, 2003
• Grant date: Dec 13, 2005
• Expiry date: Mar 7, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76834
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be significantly reduced without increasing the possibility of electrical shorts to the adjacent lines of metallization.