Method and system for forming dual gate structures in a nonvolatile memory using a protective layer

US6974995B1 · kind B1 · utility

Assignees

• Advanced Micro Devices, Inc. · US
• Spansion LLC. · US

Inventors

• Angela T. Hui · Fremont, US
• Shenqing Fang · Fremont, US
• Hiroyuki Kinoshita · San Jose, US
• Kelwin Ko · San Jose, US
• Wenmei Li · San Jose, US
• Yu Sun · Saratoga, US
• Hiroyuki Ogawa · Nagoya, JP
• Chi Chang · Redwood City, US

Key dates

• Filing date: Dec 27, 2001
• Grant date: Dec 13, 2005
• Expiry date: Dec 13, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0177

Abstract

A method and system for providing a semiconductor device is described. The semiconductor includes a core and a periphery. The method and system include providing a plurality of core gate stacks in the core, a plurality of sources in the core and a plurality of periphery gate stacks in the periphery. Each of the plurality of core gate stacks includes a first polysilicon gate and a WSi layer above the first polysilicon gate. The plurality of sources resides between a portion of the plurality of core gate stacks. Each of the plurality of periphery gate stacks includes a second polysilicon gate and a CoSi layer on the second polysilicon gate.