Sidewall formation for high density polymer memory element array
US7015504B2 · kind B2 · utility
13Cited by
7References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2003 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Nov 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K19/202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.